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CMC

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  Syntax: CMC    Byte: 1byte   Addressing Mode: Implied Addressing   Flag: Carry Working:  1. Microprocessor will allocate one byte for opcode for execution. 2. During the execution of the instruction microprocessor will complement or  perform 1's complement on content of Carry flag. Example: CMC  where  [Cy] = set = 1 After execution of CMC   [Cy] = 0                            
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INR

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Syntax: INR R Where R can be any of the general purpose registers (A,B,C,D,E,H andL) Byte: 1byte Addressing Mode: Register   Addressing Working:  1.  2.  3.  4. Flag Example: INR B   Where [B]= 10H After execution of INR B  [B]= 11H
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XCHG

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Syntax:  XCHG Rhp Where  Rhp is higher order register  the pair. ( BC or DE) Byte: 1byte Addressing Mode: Register Addressing Working:  for execution of this instruction, microprocessor will allocate first byte for opcode and the operand is register which don't need allocation. After execution of this instruction content of register pair given as operand will get swapped with content of HL register pair . Example: XCHG B where [C]= 50H &  [B] = 20 H, [H]= 80H & [L]= 60H (i.e. BC = 2050H and HL = 8060H) After execution of  XCHG B [H]= 20 H    &     [L]= 50H [B]= 80H  &     [ C ]= 60H Program: Write ALP  to swap content of BC with DE where [DE] = 4455H and  [BC] = 1122H.  Solution: Assume HL = 0000H Start:  XCHG B    ;BC= 0000H & HL = 1122H            XCHG D ; HL= 4455H& DE= 1122H            XCHG B ; HL = 00...
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